Power is the number one challenge in designing the 7nm process and the need to extend battery life to gain competitive advantage. The best way to solve power problems is to predict power consumption, find out where power is being consumed, and increase the coverage of power noise and cooling applications through the actual power distribution.
According to Semiconductor Engineering, performance, power and size area are the focus of traditional chip design. Moore's Law makes size reduction a major priority and the ability and speed requirements of microprocessors continue to increase.
With the popularity of smart phones and other mobile devices, power consumption has become the main direction of chip and system design, and the emergence of drones, Internet of Things (IoT), robots, wearables and other battery-powered electronic products has pushed Development of ultra low power chips.
Although Moore's Law is about to fail many times, it is still going on, but it has only been modified. For example, chip manufacturers are turning to composite semiconductors and 2D materials, and problems such as lithography and 3D transistor structure have also introduced new process nodes. The length of 1.5~2 years is extended to 3.5~4 years. The main culprit in increasing the difficulty of designing these chips is power, heat dissipation, noise, etc. due to power. Advanced nodes are thinner due to the thinner insulation layer, and the RC delay of the extremely thin wires is greatly reduced. The tolerance for noise and variation is greatly reduced. The power must be tightly controlled to minimize the influence of thermal energy and avoid the chip. Overheating reduces its reliability and longevity.
Oliver King, Moortec's chief technology officer, said that the new node can bring significant benefits, but because the process is not yet mature, it is more difficult to compromise between power and performance to optimize power or performance. For devices that need to be used for more than 10 years, the power goal is even more severe, and a single battery must support the entire life cycle. The new topological structure, advanced bias method, and innovative design tools are all necessary for further development. Proper semiconductor technology is an important step to achieve ultra-low power consumption. Advanced FD-SOI technology can significantly reduce power consumption, but for small and medium-sized designers, the cost and risk of moving from FinFET to FD-SOI technology are very high. high.
Battery-powered products continue to add more features and functions, and require maintaining or exceeding the battery life of previous generations, thus driving demand for power and becoming a major consideration for computationally intensive applications such as machine learning. There are also wireless technologies, such as ultra-low-power modems for Wi-Fi and 5G, so the focus of the chip design still revolves around power, performance and size, but the balance between them has changed.
Large data centers have always focused on power consumption. Server racks and storage devices require power, and heat sinks consume power. Cooling servers and other components can increase energy efficiency.
The increase in the amount of data reduces the power efficiency of moving all data to the cloud, and it also changes the user's perception of how to improve the efficiency of processing data.
Rainer Herberholz, head of the physical design business group at ARM (ARM), pointed out that ultra-low power consumption is related to the IoT edge system. Local computing hopes to reduce the power of the sensor to capture information to control the indirect cost of cloud communication and achieve higher autonomy. The best way to reduce power is to reduce the voltage, but it is not easy to do.
According to Herberholz, the main problem is the increase in timing variation and the operation of static random access memory at low voltages. The ARM ecosystem plays an important role in achieving ultra-low power goals, from fabs offering ultra-low power processes to electronic design automation (EDA), design implementations that recommend low voltage challenges, new cores and physical IP, and A new way to integrate system-on-a-chip, whether it's system-level design or software design, helps reduce power consumption.
Preeti Gupta, director of product management for ANSYS buffer transfer level (RTL), said that power behavior is highly dependent on chip activity, and that the power and thermal distribution of real-time applications such as booting the operating system can be visualized as early as possible, avoiding problems discovered later in the design process. The cost of RTL simulation is very helpful for early power noise and thermal analysis.
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