Excessive power consumption has become a major obstacle to further shrinking semiconductor process sizes, and it has seriously threatened all advances in all areas of electronics—from driving more miniaturized mobile devices to developing supercomputers.
Although the root cause lies in the eternal physical and chemical principles, engineers have developed a series of innovative technologies to alleviate the problems currently faced, and hope to help revitalize the future chip industry.
Five techniques that can be used to reduce future IC power consumption are discussed below. These technologies are currently under development and are expected to jointly address the power consumption issues that will be faced in the next decade.
Embrace collaborative design
Electronic Design Automation (EDA tools allow design teams to collaborate from the ground up to optimize low-power designs. In fact, the industry's lowest power processors and system-on-chip developers are not only optimized Architecture and materials to realize the advantages, but also use collaborative design packaging, power supplies, RF circuits and software to reduce power consumption without reducing performance or increasing costs.
"To achieve low power consumption, a comprehensive approach to overlay technology, design methodology, chip architecture and software must be used," said David Greenhill, director of design technology and EDA at Texas Instruments.
TI has used a number of advanced technologies to optimize each subsystem, raising new standards for low-power components, such as building its own process technology to balance leakage current and active current performance in shutdown mode, or using voltage And frequency expansion technology to define various power-saving modes of operation.
"The first step is to validate the product's goals from a performance and power point of view. Once these goals are determined, you can begin to use proprietary process technologies to deliver the performance you need without exceeding your device's power budget. Randy Hollingsworth, TI's 28nm platform manager, pointed out.
EDA tools have always been key to achieving these lower power goals, but sometimes it is necessary to revolve around the design loop because power estimation using traditional EDA tools is only accurate near the end of the design cycle. For future ICs, accurate power estimation must be made early in the design cycle.
Some specialized tool suppliers have picked up the baton. For example, Atrenta, Calif., introduced a tool called SpyglassPower that uses standard scratchpad transfer level (RTL) descriptions to perform power estimation, power reduction, and verification. These RTL descriptions are available from every major EDA tool at an earlier design cycle.
“Today, engineers hope to develop power estimates in earlier design cycles,†said Peter Suaris, senior engineering director at Atrenta. “You can't wait until the end of the design to estimate power consumption. You have to target power at the RTL level. Co-design and make changes to the design so that energy savings can be achieved from the start."
Atrenta claims that its dedicated energy-saving tools can estimate the final power budget with a precision of less than 20%, while power reduction tools can reduce the final design power consumption by up to 50%.
Reduce the working voltage
Miniaturized chip sizes typically reduce operating voltage for energy savings. For example, Samsung's latest 20nm 'green memory' chip reduces power consumption by reducing operating voltage from 1.5V to 1.35V.
The operating voltage of the processor and logic circuit is even lower than that of the memory, but it is inevitable that the semiconductor process must be further improved when the operating voltage is reduced below 1V. IBM, Intel, Samsung, TI, TSMC, and every other semiconductor manufacturer continue to improve processes to operate at lower voltages, but progress has slowed over the past few generations. .
The key is that the threshold voltage at which the transistor is turned on is inconsistent when using different wafers because process variations are negligible at larger sizes. Since the leakage current in the off state at a certain voltage varies greatly at different thresholds, the ideal chip actually uses a supply voltage tailored according to its characteristics.
Intel claims to have a better solution -- a solution that the company has spent nearly a decade refining. Intel uses a so-called tri-gate 3DFinFET transistor architecture that three-dimensionally surrounds three metal gates around the transistor channel, placing the transistors under the electric field of these gates. This technology can offset process variations that prevent operating voltages below 1V.
“We have successfully demonstrated our triple gate transistor structure, which reduces the operating voltage to 0.7V and can be made even lower,†said Mark Bohr, senior engineer at Intel Corporation. “These are steeper sub-threshold slopes. A fully depleted transistor that cuts off faster with less leakage current and turns on at a lower threshold."
Well-funded semiconductor manufacturers focus on simulating Intel's 3D architecture, but some startups are working on new flat-panel processes to restart the voltage-tuning process for semiconductor manufacturers that lack the time and money to perfect the 3D architecture. For example, SuVolta has invented an ultra-low voltage planar process for standard CMOS product lines.
Instead of using a 3D gate depleted transistor, SuVolta uses an undoped channel (with a doped threshold and guard band) to avoid variations in doping. The deep depletion channel process is implemented on standard planar CMOS product lines.
"By using the planar deep depletion channel process, we have successfully demonstrated that the supply voltage can be reduced to 0.6V and can be reduced even lower in the future," said Scott Thompson, chief technology officer at SuVolta.
SuVolta also secured its first licensing agreement, Fujitsu Semiconductor, which will begin mass production later this year. Further statements regarding this important licensing transaction are expected to be released later in 2012.
Intelligent adjustment function
In general, the lower the supply voltage and clock speed, the lower the power consumption. However, performance is also affected. As a result, the latest microcontrollers and SoCs are looking to use intelligent power management units to automatically adjust operating voltage and clock speed to match workloads.
"The basic idea of ​​power management is to individually adjust the supply voltage and clock speed of different parts of the chip to match its workload at any given point in time, while shutting down unused circuits." TysonTuttle, who will take over as CEO of Silicon Laboratories Said.
The power management unit is typically built as a state machine module that selectively reduces the voltage and clock speed of non-critical functions. But as semiconductor nodes become more advanced, the chip is filled with more transistors, a concept of so-called "darksilicon" - most of the chips are powered off before they need to be used. -- This may be the pioneering design philosophy for future semiconductors.
"In the future, more advanced process nodes, such as 22nm, SoC will be integrated into more transistors that can be turned on simultaneously." Rambus CTOElyTsern said, "The concept of dark silicon is to make many special-purpose functions on the chip, but in Only activate the required functions at any time, let other functions remain in a dark power-off state, and do nothing."
Intel is a leader in chip power management, allowing detailed monitoring of core temperatures at any time, allowing for increased power or reduced speed to save power by boosting the clock (turbo mode).
But not all power management functions can be ported to the chip very economically. In fact, the most intelligent power management scheme is to divide tasks between the chip and the external power management unit. "There is a constant need for external power management, because the amount of content that can be added to the chip is limited in terms of power density," said Ashraf Lotfi, CTO and co-founder of Enpirion.
Enpirion specializes in stand-alone power management units that receive commands from the processor, such as lowering the processor's voltage when the processor enters sleep mode, and quickly recovering the voltage when the processor wakes up.
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