Zedboard is the first Zynq-7000 series development board for the open source community, and the Zynq-7000 series FPGA, also known as the All Programable SoC, is a significant product line of Xilinx. Integrating high-performance processor cores in FPGAs has been a requirement of many FPGA vendors and customers. The launch of Zynq-7000 marks a breakthrough in Xilinx's SoC integration, enabling dual-core Cortex-A9 MPcore and the latest 28nm 7 series. Tight integration of programmable logic.
A simple block diagram of Zedboard, the peripheral functions of the board are all around the Zynq chip Zynq chip configuration because it is the latest chip and development kit, the data is still relatively small, and basically all of the English. To develop with an FPGA, you first need to understand the FPGA configuration process. The traditional SRAM type FPGA is configured to download the program to the FPGA at one time through the JTAG interface, external non-volatile memory (PROM, FLASH) or an external processor. The Zynq chip is different, it integrates the processor hard core and programmable logic, so its configuration startup is phased.
Stage 0: The bootROM process, the PS part of the Zynq chip has on-chip ROM and RAM. After the chip is powered on or reset, one of the processors will execute the on-chip ROM code to initialize, and determine the boot device, which will boot the device. The FSBL (first boot loader) code is copied to the on-chip RAM.
Stage 1: The boot device includes SPI FLASH, SD and JTAG. The FSBL code is customized by the user and copied to the on-chip RAM for execution. This includes initializing the PS part configuration, configuring the PL part logic, loading and executing the SSBL (second boot loader) or application.
Stage 2: The hardware has been configured since the last stage. This phase is optional and completes the Linux system boot process (U-BOOT).
Through the startup process of the Zynq chip, it can be seen that the on-chip processor is started first after power-on or reset, and then the startup mode is determined according to the MODE pin. The Zedboard can be started by the Quad-SPI FLASH, SD card or JTAG interface, as shown in the following table: Pin MIO6MIO5MIO4MIO3MIO2 Jumper JP11JP10JP9JP8JP7JTAG ModeCascade JTAG 0Independent JTAG 1Boot DeviceJTAG 000 Quad-SPI 100 SD card 110 PLL ModePLL used0 PLL bypass1
Turn on the Zedboard power supply, the program starts, because it is a very simple program, so the startup configuration process is very fast, the blue LED (LD12) is brightened to indicate that the Zynq chip configuration is completed, and the user LED is illuminated according to the logic of (10101010) after the program is executed.
The figure above shows that jumper J6 must be shorted, and the MODE jumper selects SD to start.
Use putty to monitor the serial port. The serial port parameters are set to baud rate 115200, data bit 8, stop bit 1, check none. When you are ready, you can turn on the power. The boot process from the SD card can be divided into:
After power-on, the on-chip ROM program is executed, and it is judged to be booted from the SD card after initialization.
Copy the FSBL from the SD card to the on-chip RAM, the FSBL configures the FPGA, and the blue LED (LD12) lights up to indicate that the configuration is complete.
Read SSBL from SD, start the Uboot process (start Linux), and output a Demo demo image during startup.
The serial port monitor will display the Linux boot process (you need to open the putty window before powering up). After the boot is complete, the OLED on the board will display a Digilent demo image.
After the Linux system is booted, you can now do some demonstration experiments to experience the application of the Zynq chip. 1) Control GPIO There are some script files in the /usr/bin directory to control or read the status of some peripherals. The script read_sw is used to read the state of the eight switches on the board. Entering read_sw on the command line will display the status value of the output switch (16-bit and decimal).
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