The H.264 codec IP developed by Atria Logic (including the AL-H264E-4KI422-HW encoder and the AL-H264D-4KI422-HW decoder) is ported to the Xilinx Zynq Z-7045 SoC for UHD 4K@60fps video The operation of the stream is as shown in the following figure:
H.264 codec IP design module diagram developed by ArTIa Logic
The AL-H264E-4KI422-HW encoded IP core designed by ArTIa Logic is hardware-based, feature-rich, low-latency, high-quality, and H.264 (AVC) UHD Hi422 intraframe coding. The AL-H264E-4KI422-HW encoder is paired with the AL-H264D-4KI422-HW low-latency decoder.
The IP core contains the following features:
Comprehensive modular design to support user customization and expansion
Support for intraframe H.264 and Hi422 5.1 encoding and decoding
Integrated HDMI2.0 Receive and Transmit Subsystem
Support 8/10 bit codec
Support RGB, YUV 4:2:2/4:4:4
Low latency ~0.3 seconds
Supports variable bit rate (VBR) and constant bit rate (CBR) modes
Video quality 0.99% SSIM, or 50dB PSNR or higher
Video processing subsystem for pre/post processing, including color space conversion, video scaling and density subsampling
Support Gbps Ethernet data stream output
We need to design a solution to evaluate our UHD encoding and decoding IP cores to meet 4K@60fps performance needs, then we need a flexible, powerful platform. In the end, we chose the Xilinx ZC706 evaluation kit, which is based on the Zynq Z-7045 SoC for the following reasons:
There is a ready-made FMC expansion board that provides 4K HDMI video interface: TB-FMC-HDMI 4K 2.0 version daughter card
Zynq Z-7045 SoC's rich programmable logic resources adapt to encoder and decoder IP logic to meet stringent timing requirements to meet performance requirements
The Zynq SoC processor system integrates a dual-core ARM Cortex-A9 MPCore processor, which gives us the ability to modify application driver software and custom designs, such as GUI interfaces for application design.
The H.264 encoder supports H.264 Hi422 format configuration, 5.1 standard (3840x2160p30) intraframe unique encoding. Support for 10-bit video streams This means that grayscale and color degradation will not occur from the video strip. Support for YUV4:2:2 video streaming means better color division - especially for red - which makes the image sharper. Video quality is very important for medical imaging applications.
Atria Logic UHD H.264 Encoder IP Module Diagram
Intra coding allows the H.264 encoder to achieve frame rate delay, and the macroblock pipeline architecture design further reduces latency: approximately 0.3 milliseconds. The pipeline design supports eight pixel points per clock for real-time 4K@60fps video encoding.
The H.264 encoder developed by Atria Logic uses only the Zynq Z-7045 SoC's 78% programmable logic and DSP resources, and 55% of the available RAM, leaving enough room for other necessary circuitry.
The H.264 decoder supports H.264 Hi422 format configuration, 5.1 standard (3840x2160p30) intraframe unique encoding. Like the encoder, it supports 10-bit video stream encoding, which means that there will be no grayscale or color degradation from the video strip. The decoder also supports YUV 4:2:2 video format, supports intra-frame decoding, and uses a pipelined architecture to achieve frame rate delay of the decoder.
Atria Logic UHD H.264 decoder IP module diagram
Low latency is very important for any closed-loop human/machine application. When the AL-H264E-4KI422-HW encoder and the AL-H264D-4KI422-HW low-latency decoder are connected via an IP network, the glass delay time is approximately 0.6 milliseconds (excluding transmission time). This is approximately the delay time of two frames.
The Atria Logic H.264 decoder implementation occupies only 68% of the programmable logic resources of the Zynq Z-7045 SoC, 35% of DSP resources, and 45% of RAM, leaving plenty of room for other necessary circuitry.
The HDMI subsystem consists of two main modules: the Xilinx LogicCore HDMI TX and RX subsystems, as shown in the following figure:
The HDMI Transceiver (GTX) module transmits and receives data transmitted by the serial HDMI TX and RX and converts before the serial data stream and the on-chip parallel data stream. The transceiver module implements the conversion between parallel data and serial data using the Zynq SoC high-speed GT transceiver as the HDMI PHY physical layer interface.
The TX subsystem includes a transmit module, AXI Video conversion, video timing control, and an optional HDCP module. The Axi Video stream channel transmits two to four pixels per clock to the HDMI TX subsystem and supports 8, 10, and 12-bit data encoding. This data stream conforms to the video transmission protocol defined in the AXI Design Reference Manual (UG761), which converts the input AXI-Stream to a local video format and the video timing controller to generate local video timing. Audio AXI Stream transmits multi-channel uncompressed audio data to the HDMI TX subsystem. The Zynq Z-7045 SoC's ARM Cortex-A9 processor controls the transmit module of the HDMI TX subsystem via the CPU interface.
The HDMI RX subsystem includes three AXI protocol interfaces. The video conversion bridge converts the captured local video to an AXI Stream data stream, which is output through the AXI Video interface and conforms to the protocol specifications defined in the AXI Design Reference Manual (UG761). The video timing controller measures the video timing and the received audio is sent out through the AXI Stream audio interface. The CPU interface implements control and status data communication with peripherals.
The HDCP module is optional and is not included in the standard IP core configuration.
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