The MAC sending module can encapsulate the data provided by the upper layer protocol and then send the data to the PHY through the MII interface. The sending module can receive the data frame start and the data frame end flag of the host interface module, and read the data to be sent from the external memory through the host interface, and then encapsulate the data, and then pass the carrier sense and collision detection signals provided by the PHY. When the channel is idle, the data is sent to the PHY through the MII interface in a 4-bit width, and finally the data is sent by the PHY to the network.
The sending module is composed of a CRC generating module (crc_gen), a random number generating module (random_gen), a sending counting module (tx_cnt), and a transmitting state machine (tx_statem_ module).
This module is used to calculate the CRC value of the transmitted data and add the CRC value to the Frame Check Sequence Field (FCS) of the data frame. In order to improve efficiency, and considering that the data channel of MAC and PHY is 4 bits, a 4-bit parallel CRC calculation method can be adopted in the design. A substate function can be used in the algorithm, and the shift operation is simulated by loop iteration. In this way, the transmitting module can calculate the CRC while transmitting data to the PHY, so that when the data is transmitted, the CRC value is also calculated.
Random number generation module (random_gen)If a collision is detected during transmission, the transmitting module first sends a jam code (jam) and then stops transmitting. Before the next retransmission, the sending module will perform a backoff operation first, that is, the sending module waits for a semi-random (the generated random number has a range limit) before starting to send. The random number is generated by the random number generation module. It uses the classic truncated binary exponential backoff algorithm. The backoff time is a random number related to the number of collisions. As the number of collisions increases, it is used to generate the random number. The same will gradually increase to reduce the probability of conflict.
Send count module (tx_cnt) The transmit count module consists of three counters (nibcnt), a byte counter, and a retry count counter (retrycnt). The retry count counter (retrycnt) counts the number of collisions that occur when a frame is sent. When the value of the counter reaches the maximum number of retries, it will abort the retry and discard the data in the transmit buffer. At the same time, the value of the retry counter is also used by the random number generation module to calculate the number of time slots that need to be backoff before the next retry.
The nibble counter and the byte counter are used to count the nibble and bytes, respectively, during transmission.
When the channel is busy, the sending module will wait until the nibble calculator keeps counting. When the rated waiting time is counted (twice the maximum frame length, ie 3036 bytes), the system will abandon the transmission according to the setting or wait for it (optional function). Once the channel is idle and then enters the interframe gap period (≥ 96 bit times), the southern nibble counter counts from zero. The interframe gap is divided into two parts. In the first 2/3 cycles, if the channel busy signal is detected, the nibble counter is reset and the transmitting module resumes waiting; in the last l/3 period, even if the channel is detected The busy signal, the nibble counter will not be reset, but will continue to count to ensure a fair competition channel for each station. When the value of the nibble counter reaches the frame gap period, if there is data waiting to be sent, the transmitting module starts to send data. In addition, the nibble calculator is also used for the generation of the preamble and the judgment of the short frame. When the length of the data frame is less than the minimum frame, the transmitting module must be filled or not filled according to the system settings.
The byte calculator can also be used for late collision and jumbo frames. When a lagging conflict occurs, the data being sent will be discarded. The jumbo frame is judged from the byte count of the frame content (including FCS). If the value of the byte counter is greater than the length of the maximum valid frame (1518 bytes), the sending module is based on the system setting (whether it supports super long Frame) Discard or send.
The transmit state machine module is the core of the entire transmit module and is mainly used to control the entire sending process. The sending state machine is composed of ten states such as I-die_State, Preamble_State, Data0_State, Da-tal_State, PAD_State, FCS_State, IPG_State, Jam_State, BackOff_State, and Defer_State.
After the system is reset, the transmitting module enters the Defer_State state and always detects the carrier sense (CarrierSense) signal. When the carrier sense signal becomes invalid (indicating that the channel is idle), the state machine enters the IPG_State state. After that, after waiting for an interframe gap, the state machine enters the Idle_State state. If a channel busy signal is detected during the first 2/3 of the interframe gap, the state machine will return to the Defer_State state.
After the state machine enters the Idle_State state, the transmitting module will detect the carrier sense signal and the host interface's send request. If the host module requests to send, the state machine will enter the Preamble_State state, and the sending module will notify the PHY to start transmission, and at the same time start transmitting the preamble (7 0x5), and then send the frame start delimiter (SFD, 0xd). After the state machine enters Data0_State, the transmitting module will send the lower 4 bits of the data byte (LSB nibble), and when it enters the Data1_State state, the transmitting module will send the upper 4 bits of the data byte (MSB nibble). The state machine then loops between data0 and data1 until the data is sent. When one byte remains, the host module will notify the sending module by sending a frame end signal. If the length of the data frame is greater than the minimum frame and less than the maximum frame, the state machine enters the FCS_State state, and the transmitting module adds the CRC value generated by the CRC generation module to the FCS field of the frame and sends it to the PHY. After the frame is sent, the state machine enters the Defer_State state, followed by the IPG_State and Idle_State states. The state machine then returns to the initial state to re-wait for a new send request.
If the length of the data frame is less than the shortest frame, the state machine enters the PAD_State state, and the sending module adds a padding code according to whether the system setting is after the data. The state machine then enters the FCS_State state. If the length of the data frame is greater than the maximum frame, and the system setting supports sending the super long frame, then the state machine enters the FCS_State state; if the transmission of the jumbo frame is not supported, the sending module will abandon the transmission, and the state machine directly enters the Defer state, and then It is the IPG state and finally returns to the Idle state.
In the process of transmitting data, the sending module will always check the collision detection signal (collision detected). If a collision is found and the state machine is in Preamble_State, the state machine will enter Jam_State after sending the preamble and SFD, send a congestion code, and then enter the BackOff state to wait for a retry. After that, the state machine goes back to the Idle state via Defer and IPG. If the value of the retry count counter does not reach the rated value at this time, the transmitting module will restart transmitting the previous frame and increment the value of the retry count counter by one; if a conflict is found and the state machine is in the data0, da-tal or FCS state , and does not exceed the conflict time window, then the state machine will immediately enter the Jam state to send the congestion code, then after BackOff, Defer, IPG, back to Idle, and decide whether to resend the previous data frame according to the value of the retry counter; When the time of the collision exceeds the conflict time window, the state machine will enter the Defer state, then go through the IPG to IDLE state and give up the retry.
When a frame is transmitted in full-duplex mode, no defer is performed, and no collision occurs during transmission. At this point, the transmitting module will ignore the carrier sense and collision detection signals of the PHY. Of course, the rules for interframe gaps still need to be observed between frames. Therefore, the transmit state machine in full-duplex mode does not have Jam_State. BackOff_State, Defer_State three states.
The MAC receiving module is responsible for receiving data frames. When the external PHY converts the serial data of the communication channel into parallel data of nibble length and sends it to the receiving module, the receiving module converts the nibble data into byte data, and then undergoes address recognition, CRC check, After the length judgment and other operations, the external memory is written through the host interface, and the related information of the frame is recorded in the receiving queue of the host interface module. In addition, the receiving module is also responsible for the removal of the preamble and CRC.
The receiving module is composed of a CRC check module, an address recognition module, a receiving counter module and a receiving state machine module.
The CRC check module in the receiving module can verify the correctness of the frame by checking the CRC value of the input frame. The algorithm is the same as the CRC generation module.
The address recognition module is configured to decide whether to receive the received frame, and the receiving module first receives the input frame regardless of the destination address, and then the address recognition module checks the destination address in the frame. If the MAC is set to Promiscuous mode and the destination address is a broadcast address and the broadcast frame is allowed to be received, the frame is received. Otherwise, the frame is discarded.
The receiving counter module consists of a byte counter (Bytecnt) and an interframe gap counter (IFGcnt). The byte counter counts the bytes during the reception of the frame to identify each field in the frame (preamble, destination address field, data, FCS, etc.) and to determine the jumbo frame. The interframe gap counter counts the interval between two frames to determine the start of the next frame of data. IEEE 802.3 specifies that the interval between two frames must be at least 96 bits of time (9 600 ns in 10 Mbps and 960 ns in 100 Mbps). If the interval between two frames is less than required, the frame will be discarded.
The receiving state machine is the core of the receiving module and is used to control the entire receiving process. The receiving state machine is composed of six states of Idle_State, Drop_State, Preamble_State, SFD_State, Da-ta0_State, and Data1_State.
After the system is reset, the state machine is in Drop_State. If the MII data valid signal (MRxDV) is invalid at this time, the state machine immediately enters the Idle_State state and remains in Idle waiting to receive the input frame.
After the receiving module detects the data valid signal, the state machine will enter the Preamble_State and begin receiving the preamble. Thereafter, the state machine enters SFD_State, receives a frame start delimiter of one byte, and then enters a different state according to the value of the IFGcnt counter. If the time determined by IFGcnt is greater than 96 bit times, the state machine will enter the Data0 state to receive the lower 4 bits of the byte, then the Data1 state, and receive the upper 4 bits of the byte, and then return to the Data0 state. The state machine continues to cycle between these two states until the data is received (the PHY clears the MRxDV signal) and then enters Idle to re-wait to receive new data; if the frame start delimiter is received, the IFGcnt counter determines The time is less than 96 bit times, then the state machine will enter the Drop_State state and remain in that state until the data valid signal ends (the PHY clears the MRxDV signal). After that, the state machine then goes to Idle and waits to receive new data.
If the data valid signal is cleared during the preamble, frame start delimiter, and data period, the state machine will return to Idle.
In the status information of the receiving process, the receiving error indicates that the PHY detected an error during the receiving process; receiving the invalid symbol indicates that the received frame includes an invalid (PHY unrecognizable) symbol; the lag conflict indicates that the lag is detected when the frame is received. Collision signal; an ultrashort frame indicates that the received frame is less than the shortest valid length; a jumbo frame indicates that the received frame is larger than the maximum valid frame length; a nibble alignment error indicates that the received nibble is not even (ie, framed) The length is not an integer multiple of the byte); the receive overflow indicates that the receiving module has no time to process the received data and the receive FIFO overflows.
In the status information of the sending process, exceeding the retry limit indicates that the number of retries due to the conflict exceeds the rated value; the lag conflict indicates that the conflict signal detected during the transmission of the frame exceeds the specified conflict time window; the delay indicates that The channel is detected to be busy before the frame is sent.
The MAC Control Module provides flow control in full-duplex operation. Flow control can be achieved by sending and receiving PAUSE's MAC Control Frames. When the receiving station's receive buffer (Rx FIFO) overflows and the host interface has no time to retrieve the data, the system issues a flow control request. After receiving the flow control request, the MAC sends a PAUSE control frame to cause the data sending station to suspend sending data within a specified time.
After receiving the PAUSE control frame, the data sending station can set the PAUSE timer according to the parameters in the frame. Before the PAUSE timer is decremented to 0, the transmitting module will suspend the transmission of data (except for the PAUSE control frame). After the PAUSE timer is decremented to 0, the transmitting module will resume transmitting data.
The MII management module is used to control the interface between the MAC and the external PHY for configuring the PHY and reading its status information. The interface consists of a clock signal MDC and a bidirectional data signal MDIO. The MII management module is composed of a clock generation module, a shift register module and an output control module.
The clock generation module can generate the MII management module's clock signal MDC based on the system clock and the division factor in the system settings (2.5 MHz at 10 Mbps and 25 MHz at 100 Mbps).
The shift register module can be used to write the control data of the PHY or to read out the status information of the PHY. When writing control data, the shift register converts the parallel control data into serial data according to the control signals of other modules; while reading the status information, the shift register converts the serial data of the PHY into parallel data, and other modules in the MAC. This parallel data can be written to the appropriate register.
Since MDIO is a bidirectional signal, the output control module is used to determine whether MDIO is in an input state or an output state. When MDIO is in the output state, the serial control data output from the shift register is sent to the PHY after clock synchronization; when MDIO is in the input state, the shift register converts the serial data on the data line into parallel data.
The host interface is the interface between the upper layer protocol (such as TCP/IP protocol) running Ethernet and the MAC controller. Through this interface, the upper layer protocol can set the working mode of the MAC and read the status information of the MAC. The interface can also be used for data exchange between an upper layer protocol and a MAC.
The host interface module has a set of registers that can be used to store parameters set by the upper layer protocol for the MAC and status information of the MAC. The parameters set by the upper layer protocol for the MAC include the enable of receiving the ultra-short frame, the addition of the padding code, the enabling of the transmission of the super-long frame, the addition of the CRC check value enable, the full-duplex mode or the half-duplex mode, and the holding Extended Defer Enable, Promiscuous, Receive Broadcast Frame Enable, Transmit and Receive Enable, Interrupt Source and Interrupt Enable, Interframe Clear Length, Maximum Frame and Minimum Frame Length, Retry Limit and conflict time windows, MII address and MII control commands, length of receive and transmit queues, and native MAC address.
The operation of sending and receiving data by the upper layer protocol through the MAC is mainly managed by two queues in the host interface module, and the two queues are used for queuing multiple frames waiting to be sent and multiple frames received.
The transmission queue mainly records information about a frame waiting to be transmitted, a setting of a MAC when the frame is transmitted, and status information generated after the frame is transmitted. The related information of the frame includes the length of the frame, the address of the frame in the external memory, whether the frame is ready to be sent, and whether there are other frames waiting for transmission in the queue; setting of the MAC includes interrupt enable, padding enable, CRC enable The status information generated includes the number of retries before successful transmission, the abandonment of transmission due to reaching the retry limit, the lag conflict generated when transmitting, and the delay that occurred before successful transmission.
The receiving queue mainly queues the received data frames and records each received frame information. The information includes the length of the frame, whether it is a control frame or a normal data frame, the frame contains invalid symbols, the received frame is too long or too short, a CRC error occurs, a lag conflict occurs during reception, whether the frame is received, or in the queue. Are there other frames that have been received, addresses that are stored in the external memory, and so on. This bit also has a set bit for each frame in the simultaneous queue to set whether to generate an interrupt when a frame is received.
Both the send queue and the receive queue length can be set in the control register.
According to the different backlight sources, LCDs can be divided into two types: CCFL displays and LED displays.
Misunderstanding:
Many users believe that liquid crystal displays can be divided into LEDs and LCDs. To some extent, this understanding is misguided by advertisements.
The LED display on the market is not a true LED display. To be precise, it is an LED-backlit Liquid Crystal Display. The liquid crystal panel is still a traditional LCD display. In a sense, this is somewhat fraudulent. nature! South Korea`s Samsung was once convicted by the British Advertising Association as violating the country`s advertising laws because its [LEDTV" LCD TVs were suspected of misleading consumers. For liquid crystal displays, the most important key is its LCD panel and backlight type, while the LCD panels of displays on the market generally use TFT panels, which are the same. The difference between LEDs and LCDs is only their backlight types: LED The backlight and CCFL backlight (that is, fluorescent lamps) are diodes and cold cathode lamps, respectively.
LCD is the acronym for Liquid Crystal Display, which means "liquid crystal display", that is, liquid crystal display. The LED display refers to a type of liquid crystal display (LCD), that is, a liquid crystal display (LCD) with LED (light emitting diode) as the backlight source. It can be seen that LCD includes LEDs. Corresponding to the LED display is actually a CCFL display.
(1) CCFL
Refers to a liquid crystal display (LCD) with CCFL (cold cathode fluorescent lamp) as the backlight source.
The advantage of CCFL display is good color performance, but the disadvantage is higher power consumption.
(2) LED
Refers to a liquid crystal display (LCD) that uses LEDs (light emitting diodes) as a backlight source, and generally refers to WLEDs (white light LEDs).
The advantages of LED displays are small size and low power consumption. Therefore, using LEDs as a backlight source can achieve high brightness while taking into account lightness and thinness. The main disadvantage is that the color performance is worse than that of CCFL monitors, so most professional graphics LCDs still use traditional CCFL as the backlight source.
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