The STM32's independent watchdog is driven by an internal 40Khz low-speed clock, which is still valid even if the master clock fails.
Watchdog principle: SCM system will appear in the interference of the outside world, the phenomenon of running out of the program will lead to an endless loop, watchdog circuit is to avoid this happening. The role of the watchdog is to enable the processor to automatically reset (reset the reset signal) by not receiving the dog feed signal (indicating that the MCU is already hung) for a certain period of time (via the timer counter).
Write 0xCCCC in the key value register (IWDG_KR) to start the independent watchdog; the counter starts to count down from its reset value 0xFFF. When the counter reaches the end of 0x000, a reset signal (IWDG_RESET) is generated. Whenever 0xAAAA is written in the key register IWDG_KR, the value in IWDG_RLR is reloaded into the counter to avoid a watchdog reset.
The IWDG_PR and IWDG_RLR registers are write-protected. To modify the values ​​of these two registers, you must first write 0x5555 to the IWDG_KR register. Writing other values ​​to this register will disrupt the operation sequence and the registers will be protected again. The reload operation (ie write 0xAAAA) also initiates write protection.
As long as the above three registers are set accordingly, we can start the STM32 independent watchdog. The boot process can be implemented as follows (independent watchdog related library functions and definitions are distributed in the files stm32f10x_iwdg.h and stm32f10x_iwdg.c in):
1) Cancel register write protection (write 0x5555 to IWDG_KR)
Through this step, we cancel the write protection of IWDG_PR and IWDG_RLR, so that we can operate these two registers later and set the values ​​of IWDG_PR and IWDG_RLR. The implementation function in this library function is:
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
2) Set the independent watchdog prescaler and reload value
The function to set the watchdog's frequency division factor is:
voidIWDG_SetPrescaler(uint8_TIWDG_Prescaler);//Set the IWDG prescaler value
The function to set the watchdog's reload value is:
voidIWDG_SetReload(uint16_tReload);//Set IWDG reload value
Set the watchdog's prescaler value and reload value to know the watchdog feed time (that is, the watchdog overflow time). This time is calculated as:
Tout=((4&TImes;2^prer)&TImes;rlr)/40
Tout is watchdog timeout (in ms); prer is watchdog clock prescaler (IWDG_PR value) in the range 0~7; rlr is the watchdog reload value (IWDG_RLR value).
For example, if we set the prer value to 4 and the rlr value to 625, then we can get Tout=64&TImes; 625/40=1000ms. In this way, the watchdog overflow time is 1s, as long as you are within one second, once Writing 0XAAAA to IWDG_KR will not cause the watchdog to reset (of course, writing multiple times is also possible). Here we need to remind everyone that the watchdog clock is not accurate 40Khz, so when feeding the dog, it is best not to be too late, otherwise it may happen that the watchdog reset.
3) Feed the dog with the reload count (write 0XAAAA to IWDG_KR)
The function to reload the count value in the library function is:
IWDG_ReloadCounter() ;// Reload IWDG counter according to IWDG reload register value
With this sentence, STM32 will be reloaded with the value of IWDG_RLR into the watchdog counter. That is, an independent watchdog feeds the dog.
4) Start watchdog (write 0XCCCC to IWDG_KR)
The function to start the independent watchdog in the library function is:
IWDG_Enable(); // Enable IWDG
Through this sentence, to start the STM32 watchdog. Note that IWDG cannot be closed once it is enabled! If you want to shut down, you can only restart it, and you can't open IWDG after restarting. Otherwise, the problem is still there, so let's remind everyone here that if you don't use IWDG, you don't want to open it to avoid trouble.
/**
* Initialize independent watchdog
*prer: Frequency division number: 0~7 (only low 3 bits are valid!)
*Division factor = 4*2^prer. But the maximum value is only 256!
*rlr: Reload register value: The lower 11 bits are valid.
* Time calculation (presumably): Tout = ((4*2^prer)*rlr)/40(ms).
*/
voidIWDG_Init(u8prer,u16rlr)
{
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);/*Enables writing to registers IWDG_PR and IWDG_RLR*/
IWDG_SetPrescaler(prer);/*Set the IWDG prescaler: Set the IWDG prescaler*/
IWDG_SetReload(rlr);/*Set IWDG reload value*/
IWDG_ReloadCounter();/* Reload the IWDG counter according to the value of the IWDG reload register */
IWDG_Enable();/*Enable IWDG*/
}
/**
* Feed independent watchdog
*/
voidIWDG_Feed(void)
{
IWDG_ReloadCounter();/*reload*/
}
/**
*main function
*/
Voidmain(void)
{
NVIC_Configuration();//Priority configuration
IWDG_Init(4,625);//Initialize the independent watchdog, the frequency is 64, the reload value is 625, and the overflow time is calculated as: 64*625/40=1000ms=1s
While(1)
{
Delay_ms(500);//feed the dog 0.5 seconds
IWDG_Feed();//feed dog
}
}
Second, the window watchdogWindow Watchdogs (WWDGs) are often used to monitor software faults caused by applications that are caused by external interference or unforeseen logic conditions to deviate from normal operating sequences. Unless the down counter value is refreshed before the T6 bit (WWDG-CR 6th bit) becomes 0, the watchdog circuit will generate an MCU reset when the preset time period is reached. If the down counter value of the 7-bit (in the control register) is refreshed before the down counter reaches the window configuration register (WWDG-CFR) value, an MCU reset will also be generated. This shows that the down counter needs to be refreshed in a limited time window.
Small summary:
1. There is a 7-bit down counter (WWDG-"CR) which decides when to feed the dog on this counter and window counter (WWDG-"CFR). The dog is fed early, reset - "early" reflected in the counter value (tr) window value (wr), that is, the counter value has not been reduced below the window value;
2, when 0x40 "counter value (tr) "window value (wr), this time the best feeding dog, and only feed the dog at this time is appropriate;
3. When the value of the counter changes from 0x40 to 0x3F, a watchdog reset will be generated. Of course, if the early wakeup interrupt is turned on before the reset is generated, it will enter the interrupt. In the interrupt function, we Need to feed the dog in time, otherwise it will produce a reset;
4, according to online information, in this interruption which generally do not feed the dog, usually the system before the death of the "will", such as the storage of important data. This needs to be designed according to individual needs.
In the library function, the dog feed method is used to interrupt. The relevant source code and definition of the window watchdog library function are distributed in the file stm32f10x_wwdg.c and the header file stm32f10x_wwdg.h. Proceed as follows:
1) Enable WWDG clock
The WWDG uses the clock of PCLK1. The clock must be enabled first. the way is:
RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG,ENABLE) ;//WWDG clock enable
2) Set the window value and frequency division
The function to set the window value is:
voidWWDG_SetWindowValue(uint8_tWindowValue);
This function is easy to understand because an entry parameter is a window value.
The function to set the divider number is:
voidWWDG_SetPrescaler(uint32_tWWDG_Prescaler);
This function also has only one entry parameter that is the divider value.
3) Turn on WWDG interrupts and group
The function that turns on the WWDG interrupt is:
WWDG_EnableIT() ;// open window watchdog interrupt
Next is the interrupt priority configuration, using the NVIC_Init() function.
4) Set the initial value of the counter and enable the watchdog
This step is implemented in a library function through a function:
voidWWDG_Enable(uint8_tCounter);
This function sets both the counter initial value and the window watchdog.
5) Write an interrupt service function
In the end, it is still necessary to write a window watchdog interrupt service function. This function feeds the dog and feeds the dog faster. Otherwise, when the window watchdog counter value is reduced to 0x3F, it will cause a soft reset. The EWIF bit of the status register is also cleared in the interrupt service function.
After completing the above 5 steps, we can use the STM32 window watchdog.
staticu8WWDG_CNT=0x7f;/* Saves the setting of the WWDG counter. The default is maximum. */
/**
* Initialize window watchdog
*tr:T[6:0], counter value
*wr:W[6:0], window value
*fprer: frequency division factor (WDGTB), only the lowest 2 digits are valid
*Fwwdg=PCLK1/(4096*2^fprer).
*/
voidWWDG_Init(u8tr,u8wr,u32fprer)
{
RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG,ENABLE);/*WWDG clock enable*/
WWDG_SetPrescaler(fprer);/*Sets the IWDG prescaler*/
WWDG_SetWindowValue(wr);/*Set window value*/
WWDG_CNT=tr&WWDG_CNT;/*Initialize WWDG_CNT.*/
WWDG_Enable(WWDG_CNT);/* Enables watchdog and sets counter. */
WWDG_ClearFlag();/* Clear early wakeup interrupt flag */
WWDG_NVIC_Init();/* Initialize window watchdog NVIC*/
WWDG_EnableIT();/*Open window watchdog interrupt*/
}
/**
* Window Watchdog Interrupt Service Routine
*/
voidWWDG_NVIC_Init(void)
{
NVIC_InitTypeDefNVIC_InitStructure;
NVIC_InitStructure.NVIC_IRQChannel=WWDG_IRQn;/*WWDG Interrupt*/
/* Preemption 2, child priority 3*/
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=2;
NVIC_InitStructure.NVIC_IRQChannelSubPriority=3;
NVIC_Init(&NVIC_InitStructure);/*NVIC Initialization*/
}
/**
* Reset the value of the WWDG counter
*/
voidWWDG_Set_Counter(u8cnt)
{
WWDG_Enable(cnt);/* Enable watchdog, set counter. */
}
/**
* Watchdog interrupt service routine
*/
voidWWDG_IRQHandler(void)
{
WWDG_Set_Counter(WWDG_CNT);
WWDG_ClearFlag();/* Clear early wakeup interrupt flag */
LED1=~LED1;/*LED status flip*/
}
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