This article is mainly about the related introduction of lpc2000, and focuses on the principle and function of lpc2000 to elaborate in detail.
lpc2000The vectored interrupt controller (VIC) of the LPC2000 series supports 32 interrupt request inputs, that is, supports 32 interrupt sources, see Table 5.1. These 32 interrupts are called VIC channel 0, VIC channel 1, ..., VIC channel 31 in order.
Each VIC channel supports software interrupts and hardware interrupts, that is, each interrupt can be generated by software or hardware interrupts, and the software interrupts and hardware interrupts on the corresponding channels are in a logical OR relationship. The software interrupt can be generated by setting the corresponding bit of the VICSoftInt register, or can be cleared by setting the corresponding bit of the VICSoftIntClear register.
LPC2000 has 3 types of interrupts: FIQ, vector IRQ and non-vector IRQ. The LPC2000 series can set the above 32 interrupt sources to any of these three types of interrupts by setting the two types of registers VICIntSelect and VICVectCntlx (x=0, 1, …, 15). among them,
The fast interrupt request FIQ has the highest priority. It is recommended to allocate only one interrupt request to FIQ to reduce the delay of the Zhongyuan processing program. Of course, VIC supports multiple FIQ interrupts.
Vector IRQ has medium priority. Up to 16 of 32 requests can be allocated at this level. Any one of the 32 requests can be allocated to any one of the 16 vector IRQ slots. Among them, slot0 has the highest priority, while slot15 is the lowest priority.
Non-vector IRQ has the lowest priority.
How to initialize an interrupt source as one of the three types of interrupts
Use the VICIntSelect interrupt selection register to allocate 32 interrupt requests as FIQ or IRQ (including vector IRQ and non-vector IRQ); use VICVectCntlx (x=0, 1, …, 15) to select one of the 32 interrupt requests as a vector IRQ and set this interrupt request to IRQ slotx (x corresponds to x in VICVectCntlx). If an interrupt source is set to IRQ, but not enabled by VICVectCntlx, the interrupt source will be defaulted to non-vectored IRQ.
Interrupt handling process The interrupt handling process is as follows:
Initialization: Set the interrupt source to one of the three interrupt sources, set the interrupt address, enable the interrupt, and then run the user program normally;
When an IRQ interrupt is generated, VIC will set the VICVectAddr register to the address of the corresponding interrupt service program according to the interrupt source, switch the processor working mode to IRQ mode, and jump to the IRQ interrupt entry 0x00000018;
Use "LDR PC, [PC, #-0xFF0]" at 0x00000018 in the abnormal interrupt vector table to make the program jump to the address saved in the memory (0x00000018+8-0x00000FF0=0xFFFFF030). 0xFFFFF030 is the VICVectAddr register address. That is to say: through this instruction, the program jumps to the address of the interrupt service routine pointed to by the VICVectAddr register;
The interrupt service routine executes the corresponding interrupt processing and clears the interrupt. It is recommended to use the __irq keyword to define the interrupt service routine;
After the interrupt service is completed, you can return to the original interruption point. When returning, switch the working mode of the processor at the same time.
Note: Before exiting the interrupt, you must write 0 to the VICVectAddr register to notify the end of the VIC interrupt; it is recommended to use the __irq keyword to define the interrupt service routine. In this case, the function will automatically switch the processor working mode, but the function cannot return parameters or Numerical value.
IRQ interrupt
There are two types of IRQ interrupts: vectored IRQ and non-vectored IRQ interrupts. When IRQ interrupts are generated:
If it is a vectored IRQ interrupt, since VIC has already loaded the IRQ service program address VICVectAddrx (x=0,1,...,15) of the highest priority request into VICVectAddr before, the program jumps into the interrupt service program to continue execution.
If it is a non-vector IRQ interrupt, VIC provides the default service program address VICDefVectAddr. The IRQ interrupt entry program can obtain the address by reading the vector address register VICVectAddr of the VIC, and then jump to the corresponding service program to continue execution. The default service program is shared by all non-vector IRQs, and the default service program can read the IRQ status register to determine which IRQ is activated.
The working principle of lpc2000Embedded processor is the core part of embedded system hardware. Philips has introduced more than ten ARM7-based high-performance and low-power LPC2000 series microcontrollers to meet the growing embedded market demand. The operating frequency of LPC2000 series microprocessor is 60MHz, adopting 32-bit RISC based on ARMTDMI core. The peripheral interface of LPC2000 is very rich, including UART, SPI, I2C, CAN, ADC, PWM, RTC, etc.
This series of microcontrollers LPC2114/2124/2119/2129/2194, LPC2210/2212/2214, LPC2290 /2292/2294 use the on-chip memory load module to realize the "zero-wait access" high-speed flash memory function, which improves the efficiency of instruction execution. Provides enhanced communication functions and on-chip code protection mechanism on the basis of high performance and low power consumption. Because of the built-in wide-range serial communication interface, they are also very suitable for communication gateways, protocol converters, embedded soft modems, etc. The 6-channel PWM is more suitable for complex motor control applications.
LPC2000 series microcontrollers can realize high-speed flash memory with zero wait access, which is mainly due to the on-chip memory acceleration module. Figure 2 is a block diagram of the memory acceleration module. The 128-bit width flash memory array interfaces with the processor through a separate local bus, and can provide four 32-bit instructions for the ARM core per cycle. This allows the MCU to directly execute instructions from the flash memory without going through the wait state, thereby eliminating the waiting time when reading the general flash memory. In order to solve the change of the instruction sequence and the waiting time caused by the different processing of instructions and data, the module has implemented three functions: prefetch buffer, data bypass and jump tracking buffer to avoid data read/write disturbing the address sequence. The joint work of blocks, and two sets of 128-bit wide memories are used for parallel access to eliminate delays.
The function of the memory acceleration module depends on the size of the system clock. The access time of the LPC2000 series on-chip flash memory is 50nS. For applications where the system clock is not higher than 20MHZ, the contents of the flash memory can be read in one cycle, and there is no need to use a memory acceleration module at this time. The higher the clock frequency, the more the system performance will be affected when the code in the flash memory is directly executed. At this time, the memory acceleration module can be enabled to obtain a speed close to 4 times the speed, which truly realizes zero-wait high-speed flash memory. Since LPC2000 can execute instructions directly from flash memory, there is no need to transfer code to SRAM during boot, which not only saves time-consuming and energy-consuming system startup steps, but also saves expensive SRAM.
The on-chip flash memory can be programmed in several ways: through the built-in serial JTAG interface, through the serial port for in-system programming (ISP), or through in-application programming (IAP).
Vector interrupt controller
The vector interrupt controller of the LPC2000 series can support up to 32 interrupt requests, and can be programmed into 3 categories according to needs: FIQ, vector IRQ and non-vector IRQ. The fast interrupt request (FIQ) requires the highest priority. Vector IRQ has medium priority. This level can allocate 16 of 32 requests. Non-vector IRQ has the lowest priority. This programmable allocation mechanism means that the interrupt priority of different peripherals can be dynamically allocated and adjusted. For any vector interrupt, once a request is issued, the CPU can read the VIC in one cycle and jump to the entry address of the corresponding interrupt service routine, which reduces the interrupt delay to a minimum.
Method for programming on-chip flash of LPC2000 series microcontroller1. Introduction to LPC2000 Flash
The Flash memory system contains 16 sectors of 128kB Flash devices and 17 sectors of 256kB Flash devices. The flash memory starts at address 0 and increases upward. The Flash boot loader also provides ISP and IAP programming interfaces for the on-chip Flash memory. IAP, ISP and RealMonitor programs are all located in the boot sector. The boot sector exists in all devices. The ISP and IAP commands do not allow write/erase/run operations on the boot sector. In 128kB Flash devices, only 120kB Flash is available for user programs. The device contains a total of 256kB of Flash, of which 248kB of Flash can be used by user programs. Boot Block is generally located at the top of the on-chip Flash memory. In 128kB Flash, it is the 16th sector (the corresponding sector number is 15), and in 256kB Flash, it is the 18th sector (the corresponding sector number is 17). The Flash memory sector occupied by Boot Block cannot be used to store user data.
The LPC2000 series provides in-application programming IAP, and the end-user code directly executes in-application programming (IAP) to erase and program the on-chip Flash memory. Falsh can erase and write 10,000 times, and the programming time for 512-byte rows is 1ms. Single sector or whole chip erasing time is 400ms.
Flash memory cannot be accessed during write or erase operations.
IAP commands that perform Flash write/erase operations use the 32-byte space at the top of the on-chip RAM. If IAP programming is allowed in the application, the user program should not use this space.
Many 8-bit microcontrollers have the concept of a page. The page is the smallest unit of Flash programming. The content of a page can be erased and programmed at a time. Because the page contains fewer bytes, Flash is used as EEPROM in this case Flexibility will be great. The LPC2000 series does not have the concept of a page. It only has the smallest Flash programming unit, which is a sector. That is, even if the user only modifies one byte, the 8K Flash needs to be erased first.
The process of treating Flash as EEPROM is actually a process of reading-modifying-writing Flash.
2. Write data to Flash
Flash must follow the process of selecting sectors, erasing, selecting sectors, and writing. Specific to the programming of the program, the following codes must be successively:
SelSector(1,1); // select sector 1
EraseSector(1, 1); // Erase sector 1
SelSector(1,1); // select sector 1
for(i=0;i《512;i++)
sourceï¼»iï¼½=0x41;
RamToFlash (0x00002000, (uint32) source, 512); // write data to sector 1
Pay attention to the following points when applying:
1) If no sector is selected before writing, it cannot be written correctly.
2) If there is no erase before writing, the writing is incorrect.
3) Write at least 512 bytes, and the number of bytes written should be 512 or 1024 or 4096 or 8192.
4) Flash cannot be accessed during erasing and writing, which is the reason why IAP wants to close the interrupt. Turning off the interrupt can be implemented with the following statement: __asm{MSR CPSR_c, #0xdf}, corresponding to this, turning on the interrupt can be achieved with the following statement: __asm{MSR CPSR_c, #0x5f}.
In addition, people often ask how to define a constant value at a specific address in Flash. I think this function is not very practical, because the smallest unit of erasure is 8K. It is better to write data directly to an address in Flash. The address is in an empty sector, and both read and write use this address as the base address. Since the compiled code is close to the bottom, you can check the amount of compiled code, and then select the upper address as the variable area for use. If you really want to define the array at a specific location in Flash, it seems that you can use scatter loading.
3. Read data from Flash
Reading data from Flash is relatively simple. You can define a pointer variable that points to a specific Flash address. For example, it can be written as follows:
uint32 i;
uint8 * p;
p=(uint8 *)0x1C000;
for(i=0;i《400;i++)
{
Puthexbyte(*(p++));
}
4. Flash encryption
Code read protection This is a feature of Bootloader revision 1.61. Code read protection is enabled by writing 0x87654321 (2271560481 in decimal notation) to the Flash address unit 0x1FC (user Flash sector 0). The address unit 0x1FC is used to allow some space to be reserved for the fiq exception handler. When the code read protection of the JTAG debug port is enabled, the external memory boot and the following ISP commands will be disabled:
ï¬ Read memory
ï¬ Write RAM
ï¬ Operation
ï¬ Copy RAM content to Flash
When the above ISP command terminates, it returns CODE_READ_PROTECTION_ENABLED. When the code read protection is enabled, the ISP erase command only allows the contents of the user sector to be erased. This restriction is not available when the code read protection is disabled. IAP commands are not affected by code read protection.
RelInFlash using the project template will be automatically encrypted.
5. Points to note when using engineering templates
Pay attention to the following points when using ZLG's project template:
1) Modify the stack, the initialization stack in the STARTUP.S file is StackUsr-20*4
2) Set the compilation parameter -apcs/intervork, you need to pay attention to modify the language settings/ARM C Compiler/ATPS. The language setting I accidentally selected at the beginning was ARM Assembler, but after running the program, it was wrong when I wrote Flash. You have to choose the correct language setting.
3) Variable definition. Since at least 512 bytes are written at a time, it is best to define the variable for read and write operations as uint32 type. One mistake I made was to define the variable as uint8 type, as shown below:
uint8 i;
for(i=0;i《512;i++)
sourceï¼»iï¼½=0x41;
RamToFlash (0x00002000, (uint32) source, 512); // write data to sector 1
The result is conceivable. It has been running in the for loop and cannot jump out. This gives us an illusion that IAP is not easy to use.
ConclusionThis is the end of the related introduction about lpc2000. Please correct me if there are any deficiencies.
Related reading recommendation: Programming and Application of LPC2000 Series CAN Acceptance Filter
Related reading recommendation: Application of CAN Bus Acceptance Filter of LPC2000 Series
Tobacco control has been a common global concern, while the traditional tobacco industry gradually, new tobacco has become the new strategic layout of tobacco giants. In this context, the emergence of e-cigarettes has further led to the replacement of traditional tobacco. At present, there are already a thousand different types of e-cigarettes, which have undergone several stages of development. The e-cigarette we are introducing today is the CBD pod systewm, a new type of e-cigarette. In this article we will combine the characteristics of the CBD with a brief analysis of it.
·Anti-anxiety
According to scientific studies,CBD can help depressed patients reduce their anxiety. The use of CBD can help maintain endogenous cannabinoids at a reasonable level, making the patient feel good and happy physically, and without any dependence.
·Anti-ageing
CBD is very powerful in anti-ageing. As a non-psychoactive component of the cannabis plant CBD inhibits the glutamate toxic response of cortical neurons and suppresses excessive oxidative stress, helping the body to achieve anti-ageing effects.
·Anti-inflammatory
CBD reduces the free radicals that cause neurodegenerative diseases and reduces swelling through its anti-inflammatory effects. In addition, CBD stimulates appetite and relieves pain.
China Disposble Vape Pen,E-Cigarette Cbd Vaporizer,Best Disposable Cbd Vape Pen,Disposable Cbd Vape
Shenzhen MASON VAP Technology Co., Ltd. , https://www.cbdvapefactory.com